A full adder is one of the basic circuits used in various architectures. Different techniques have been employed in these architectures to implement carry propagation in an adder chain. FIG. 1 illustrates a configurable logic block (CLB) of a conventional PLD made by Xilinx, Inc. This CLB is described in more detail in U.S. Pat. No. 5,546,018. As shown, the Xilinx CLB includes four four-input function generators F, G, H, J each comprising look up tables for implementing one bit of an arithmetic function of two variables which are received on the input terminals 0,1,2,3 of each function generator. A one-bit addition of two variables can be performed by using the carry multiplexer for the carry bit and the exclusive OR gate for the sum bit.
FIG. 2 illustrates a logic array block of a conventional PLD made by Altera, Inc. This LAB is described in more detail in U.S. Pat. No. 5,761,099. This device also comprises a four-input look up table, which can be configured to perform one bit of an arithmetic operation of two input variables. A one-bit addition of two variables, along with the carry, can be performed in the LUT.
The carry circuit in the Xilinx PLD can be utilized to implement functions such as AND, OR, XNOR, etc. as described in U.S. Pat. No. 6,353,920. However, the carry circuit cannot be used in isolation. The carry circuit has to be used along with the LUT for the implementation of each of the functions. Furthermore, both of the architectures use a four-input LUT (and some carry circuitry) to generate a sum and a carry bit.